// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.1 (win64) Build 6140274 Thu May 22 00:12:29 MDT 2025
// Date        : Sun Oct 19 21:48:12 2025
// Host        : wwws12 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               d:/FPGA_Proj/pynq_test_1019/pynq_test_1019.gen/sources_1/bd/linux_board/ip/linux_board_board_test_0_0/linux_board_board_test_0_0_stub.v
// Design      : linux_board_board_test_0_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7z020clg400-1
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* CHECK_LICENSE_TYPE = "linux_board_board_test_0_0,board_test,{}" *) (* CORE_GENERATION_INFO = "linux_board_board_test_0_0,board_test,{x_ipProduct=Vivado 2025.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=board_test,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* IP_DEFINITION_SOURCE = "module_ref" *) (* X_CORE_INFO = "board_test,Vivado 2025.1" *) 
module linux_board_board_test_0_0(sys_clk, btn, sw, led, rgbled0, rgbled1)
/* synthesis syn_black_box black_box_pad_pin="btn[3:0],sw[1:0],led[3:0],rgbled0[2:0],rgbled1[2:0]" */
/* synthesis syn_force_seq_prim="sys_clk" */;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 sys_clk CLK" *) (* X_INTERFACE_MODE = "slave" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME sys_clk, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input sys_clk /* synthesis syn_isclock = 1 */;
  input [3:0]btn;
  input [1:0]sw;
  output [3:0]led;
  output [2:0]rgbled0;
  output [2:0]rgbled1;
endmodule
